Storage of data in dense memories requires the use of a plurality of "memory cells". Each of these memory cells is comprised of a number of active devices and control lines for access thereto. These control lines allow for reading of data stored therein and writing of data thereto. Heretofore, memory cells such as cross coupled memory cells have been utilized which require two bit lines and a word line in addition to four active devices or transistors. By properly biasing the bit lines and the word lines, data can either be read out of the memory cell or written to the memory cell.
Another type of memory cell that has been previously utilized is the Schmitt trigger memory cell which is described in "New Circuit Configuration For A Static Memory Cell With An Area of 880 .mu.m.sup.2 ", Schrader and Meusberger, IEEE Journal of Solid State Circuits, Vol. SC-13 pp. 345-351, June 1978. In a Schmitt trigger memory cell, five devices are utilized with one of the devices being the control device for gating a storage node internal to the device to an external bit line. The Schmitt trigger memory cell only utilizes one bit line as compared to the two bit lines of the cross coupled memory cell. With the use of only one bit line, less area is utilized. However, one disadvantage to the current Schmitt trigger memory cell is the response time verses power requirements. A driving transistor is utilized to supply current to the storage node to raise the voltage level thereon to a high voltage level representative of a high logic state. A current source is utilized to supply current to the gate of the transistor to maintain it in a continuous conduction state. By diverting current from this current source, the voltage at the storage node can be switched to a logic low state. In making a transition from a logic low to a logic high state, the response time of the memory cell is a function of the response time of the driving transistor supplying current to the storage node. This response time is determined by the size of the gate capacitance and the current available for charging thereof.
In view of the above disadvantages, there exists a need for circuitry to reduce the response time of a Schmitt trigger memory cell without requiring a decrease in the gate capacitance of the driving transistor or an increase in the static current in the low logic state.